Padmanabhan, T.R and Sundari, Bala, S.T  <br/><br/>
Design through verilog HDL  

 - Wiley india   New Delhi   2010 
 - XII, 455p.   399 
<br/><br/><label>ISBN: </label>9788126519316 
<br/><br/><label>Subjects--Topical Terms: </label><br/>VHDL 
<br/><br/><label>Dewey Class. No.: </label>621.392 PAD